| Employment Type | Contract |
|---|---|
| Location | Wiltshire, Salisbury |
| Industry Sector | Defence |
| Start Date | ASAP |
| Salary/Rate | £300 per day |
| Reference | 318518-KW |
| Date Advertised | Yesterday - 00:01 |
A CIC Filter Architecture with time-varying coefficients has been identified as a candidate algorithm, but this requires design optimisation to realise the required performances .
The task required is the implementation of algorithms to resample a digital signal represented at a number of different sample rates down to a common lower sample rate. A CIC Filter Architecture with time-varying coefficients has been identified as a candidate algorithm, but this requires design optimisation to realise the required performances. Other algorithms may be proposed for study, and compared with the baseline CIC architecture as part of this work, but must bear in mind the intention to target the implementation on an FPGA.
Initially the algorithm will be written in a high-level language (eg MATLAB or SIMULINK) for use on a general purpose computer, but an understanding of the implications for implementation in VHDL must be taken into account.
Preferred skills:
Digital Signal Processing; CIC filter design
knowledge of state-space diagrams
Software knowledge in MATLAB, SIMULINK, (or other suitable high-level language)
Ability to explain approach to both the expert and non-expert (software user level)
Proven track record for delivery to time, quality and cost
knowledge of VHDL and FPGA implementations preferred but not essential.
Due to the nature of the business all applicants must have current valid SC clearance
